1. Field of the Invention
This invention relates to a semiconductor integrated circuit having static memory cells. More particularly, the invention relates to a semiconductor integrated circuit that can suppress or mitigate the occurrence of a sub-threshold leakage current by reducing a potential difference of a pair of power source nodes of a static memory cell and to a technology that will be effective when it is applied to SRAM (static random access memory), for example.
2. Description of the Related Art
A patent document 1, listed below, describes a low potential supply circuit for shifting a power source potential or a ground potential of a memory array in a static operation mode. This low potential supply circuit has a parallel circuit of a switch and a diode. The switch is turned OFF in the static operation mode such as a standby mode and the ground potential of the memory array rises by a potential corresponding to a barrier potential component of the diode to thereby reduce a potential between a power source node and a ground node of the memory cell. Consequently, a useless consumed current in the static operation mode can be reduced without impeding a circuit operation in a dynamic operation mode.
A patent document 2, listed below, describes a technology that intermittently brings a ground power source line of a flip-flop constituting a memory cell into a floating state at the time of standby of the memory cell. Because the ground power source line is intermittently brought into the floating state, the potential of the ground node of the memory cell rises and an OFF leakage current (sub-threshold leakage current) of the memory cell can be decreased.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2002-197867
Patent Document 2: Japanese Laid-Open Patent Publication No. Hei 9 (1997)-185887
The inventor of the invention has examined disadvantages that will occur when the potential difference between the power source node and the ground node of the memory cell is decreased so as to decrease the sub-threshold leakage current during standby. A data holding voltage of the memory cell drops when the potential difference is decreased. When the drop of the power source potential of the circuit or the rise of the ground potential of the circuit occurs under this state due to fluctuation of the power source voltage, the data holding voltage applied to the memory cell becomes further smaller. The drop of the data holding voltage enhances the influences of fluctuation of a substrate voltage and soft errors resulting from α rays and the data held by the memory cells is more likely to under go breakdown. The prior art technologies listed above do not take these problems into account.